An Architecture for Parallel Interpretation of Abstract Machine Languages

An innovative central processor architecture is described that exploits the innate parallelism found in the machine language interpretation process. A new instruction encoding method, that facilitates the design of pipelines, is used to design the instruction sets of the controller, memory, and execution units. The problem of incorporating pipelined parallelism with other forms of implicit parallelism is discussed. Performance profiles of nine benchmark programs, obtained by using a cycle-level simulator, show the advantages of the described architecture for parallel over an equivalent architecture for serial interpretation. Performance measurements of representative benchmark programs show that a speed up of about two is achieved compared to the traditional sequential machine language interpretation on a single processor.